1. Field of the Invention
The present invention relates generally to semiconductor testing devices and componentry. More specifically, the present invention relates to devices and systems configured for operation and testing of random access memory (RAM) modules.
2. State of the Art
Semiconductor integrated circuit (IC) devices are manufactured on wafers or other substrates of semiconductor material. Conventionally, many IC devices are manufactured on a single substrate and individual devices or groups of IC devices are cut or “singulated” from the substrate and packaged. The IC devices are tested at various points during the manufacturing process, e.g., while they are still in substrate form, in bare die form (after singulation but prior to packaging), and after packaging.
Testing may be directed towards detection of flaws or errors regarding one or more facets of semiconductor fabrication. For example, one stage of testing concerns the physical structure of the IC device. Such testing may include the use of various techniques known in the art such as emission microscopes or X-ray analysis. Testing of the structure typically focuses on whether discernible errors or flaws have developed during the physical formation of the semiconductor die. Such flaws may be the result of one or more processing steps improperly performed such as over-etching. Flaws are also developed as a result of contaminants introduced during the fabrication process. Indeed, numerous process factors exist which may influence the introduction and development of such flaws or errors.
Another facet of testing concerns the functionality and performance of the IC device. This typically involves connecting the IC device to an external circuit such that a signal or combination of signals may be passed through the device. The response by the IC device to the signal is then monitored and output values compared to values expected to be obtained from a properly functioning IC device of that design. Tests may involve a particular signal or combination of signals being delivered repetitively, perhaps under extreme environmental conditions (temperature, voltage, etc.) in order to identify an IC device which would fail after a shorter than satisfactory period of operation. Other tests may involve the delivery of a number of different signals or signal combinations in sequence. One method, compression testing, for testing a memory device includes delivering the same signal or signal combination to multiple identical subsections of the memory device simultaneously and comparing the values read from the subsections. If all of the respective read values match, the test has been passed, while a mismatch between respective values read from any of the subsections indicates a device malfunction and failure of the test.
An obvious intent of IC device testing is to produce an IC device having verified reliability and quality. While this objective is significant, the efficiency with which testing is performed is also an important concern, as speed of testing is a limiting factor in fabricating IC devices and assemblies. It then becomes desirable to reduce testing time whenever possible without compromising the integrity of the testing process. A reduction in test time without a sacrifice in quality results in lower manufacturing costs by increasing throughput and thus yield. Reduced manufacturing costs are very desirable in that they may ultimately lead to higher profits for a company or its shareholders, as well as provide a cost savings to the consumer by enabling price reductions.
One method of reducing test time without compromising the integrity of the testing process is to perform batch tests. In other words, numerous IC devices are tested coterminously instead of sequentially, one at a time. An example of such testing, with specific regard to memory devices, may be better understood with reference to FIG. 1. A testing apparatus 10 may include a plurality of motherboards 12 housed in a holding device such as a cabinet or a frame 14. A plurality of memory devices, such as RAM memory modules 16, are appropriately coupled to individual memory sockets 18. Each memory socket 18 is operatively coupled to a motherboard 12 with each motherboard 12 including multiple memory sockets 18. Thus, each motherboard 12 is capable of accommodating several memory modules 16 during a given testing operation.
With the memory modules 16 in place, electrical or functional testing of the memory modules 16 is conducted. As described above, the motherboards 12 provide a signal or signals to the RAM memory modules 16 and then are employed to monitor the responsive output of each RAM memory module 16. The configuration as described above allows numerous memory modules 16 to be tested in a relatively short amount of time. However, while the above-described system allows for a greater quantity of devices to be tested at a given time, the turnaround time in removing tested modules and subsequent installment of untested modules is less than optimal.
One problem with a testing apparatus configuration as illustrated in FIG. 1 is that, in a structure configured to maximize the number of memory modules 16 being tested at a given time, the ability to rapidly change the memory modules 16 becomes hampered. This primarily results from the density and close proximity of the motherboards 12 within the cabinet 14 combined with the locations and configurations of the memory sockets 18 on the motherboard 12. A typical motherboard 12 is configured such that the memory sockets 18 are mounted along a planar surface of the motherboard 12, causing the memory modules 16 to extend away from the motherboard 12 in a perpendicular manner. Furthermore, the memory sockets 18 are typically fixed in their locations by mechanical means including, for example, soldering. Therefore, to extract a memory module 16 from a memory socket 18, the memory module 16 must be moved in a direction perpendicularly away from the planar surface of the motherboard 12. However, in a testing apparatus 10 where the motherboards 12 are configured in close proximity to each other and movement of memory modules 16 is transverse to the plane of the motherboard 12, removal of a memory module 16 becomes rather difficult and time consuming.
For example, still referring to FIG. 1, distance “A” represents the distance between the top of a memory module 16 and an adjacent motherboard 12. Distance “B” represents the minimum distance that the memory module 16 must travel to be removed from the memory socket 18 (i.e., the distance required for the bottom of the memory module 16 to clear the top of the memory socket 18). It may often be the case that distance “B” is greater than distance “A.” In such instances, it becomes physically impossible to remove the memory modules 16 (or insert them) unless the motherboards 12 are first removed from the frame 14. With a plurality of motherboards 12 each having a plurality of memory sockets 18, replacement of the memory modules 16 thus becomes a laborious task. Even if the motherboards 12 are arranged so that distance “A” becomes larger than distance “B,” it remains difficult for an individual to maneuver his or her hands between the motherboards 12 and complete the task of insertion or removal of the memory modules 16 with any degree of efficiency.
In view of the shortcomings in the art, reducing the time required for the removal and replacement of memory modules during the testing process would be advantageous.
It would also be advantageous to provide an apparatus or system which could accommodate the use of an automated handler to remove and replace memory modules during the testing process. Such a system should be flexible and adaptable to a user's needs, as well as simple to implement and operate.